What Is UVM Verification?

Universal Verification Methodology (UVM) verification is a standardized form of design verification used in FPGA and ASIC design projects. UVM was facilitated by Accellera, a standards organization, and was based on ASIC verification methodologies developed by prominent companies in the electronic design automation industry.

The main goal of UVM verification is to improve design verification efficiency through the use of reusable verification components. However, manually creating and debugging UVM verification components can still require a significant amount of effort, especially for new algorithmic content, and the complexity of UVM can be an obstacle to its adoption by design teams.

Since many algorithms developed for ASIC and FPGA design projects begin as MATLAB^® code or Simulink^® models, design teams can reduce testbench development efforts by generating UVM verification components directly from the MATLAB or Simulink source. With the ASIC Testbench for HDL Verifier™ add-on, you can automatically generate SystemVerilog DPI components from MATLAB code or Simulink models. These components can be used as golden reference checker models in a UVM verification scoreboard, as behavioral digital or analog component models in mixed-signal simulation, or as sequences that serve as a UVM verification stimulus.

HDL Verifier can also generate complete UVM verification environments directly from Simulink models. HDL Verifier generates SystemVerilog UVM sequence, driver, monitor, and scoreboard components from models of testbenches. It also produces SystemVerilog files for a behavioral design under test (DUT). The behavioral DUT can then be replaced with manually coded RTL or with RTL generated using HDL Coder. Generated UVM verification environments may be used with Siemens^® ModelSim^® or Questa^®, Cadence^® Xcelium™, or Synopsys^® VCS^®.

For additional information, see HDL Verifier.