In production, FPGA, ASIC, and SoC projects, RTL verification typically consumes the most time and effort of any task. Despite this effort, bugs still make it into silicon at a higher rate than desired. One of the root causes is the communication gap between algorithm design, which often starts in MATLAB® or Simulink®, and RTL design and verification. New algorithms are too complicated to rely on specification documents and hand-writing code.
This video presents a solution to this communication gap, presented in the order in which we typically see our customers adopt these new techniques:
- SystemVerilog DPI component generation: Rather than relying on the algorithm engineer to write a specification document that the verification team must then interpret and write test cases and reference models for, you can automatically generate models from MATLAB or Simulink for your SystemVerilog testbench. And if the specification changes, you make the change in the algorithm, test it, and re-generate the models.
- Cosimulation: When you need to debug issues between your RTL design, testbench, and system- or algorithm-level design, you can cosimulate MATLAB or Simulink together with your RTL simulator. This provides full visibility into the algorithm and the RTL simultaneously, enabling the algorithm engineer to collaborate directly with the verification and hardware design engineers.
- Early verification and validation: Many customers have started to refine their algorithms with more hardware detail, such as streaming behavior, fixed-point data types, and hardware architecture. They then build a reusable and automated test environment, embed assertions, and measure coverage.
This phased approach to adoption yields benefits for the verification team almost immediately, and over the long term encourages collaboration between system/algorithm design, hardware design, and hardware verification, leading to a more robust and agile development process.
