Verifying Algorithms on FPGAs and ASICs

Developing new FPGA and ASIC designs involves implementation of new algorithms, presenting verification challenges for algorithm developers, hardware designers, and verification engineers.

Read this ebook to learn how to address verification challenges and reduce development effort by using MATLAB^® and Simulink^® for:

Creating golden reference models
Using reference models for design verification
Testing algorithm implementation on FPGA development boards
Performing top-down design and verification of analog/mixed-signal designs
Adopting DO-254 and ISO 26262 certification workflows to meet functional safety requirements

Learn More

Reuse of System-Level Verification Components within Chip-Level UVM Environments - Conference Paper
Introduction to FPGA Verification with MATLAB and Simulink (44:17) - Video
HDL Verifier - Overview

Getting Started Using MATLAB and Simulink for FPGA, ASIC, and SoC Development

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