DPI Generation for Simulink Subsystem

Generate SystemVerilog DPI component from Simulink^® subsystem

You can use a DPI component generated from a Simulink subsystem in two ways :

Export SystemVerilog DPI Component — You can integrate this component into your HDL simulation as a behavioral model. The component generator supports test points and tunable parameters. You can also generate a SystemVerilog test bench that verifies the generated DPI component against data vectors from your subsystem. See Generate SystemVerilog DPI Component.
Generate SystemVerilog DPI Test Bench (with HDL Coder™) — Use this test bench to verify your generated HDL code using C code generated from your entire Simulink model, including the DUT and data sources. See Verify HDL Design Using SystemVerilog DPI Test Bench (HDL Coder).

See DPI Component Generation with Simulink.

To use this functionality, download and install the ASIC Testbench for HDL Verifier add-on. This feature also requires Simulink Coder™.

Apps

HDL Verifier

Generate HDL verification artifacts and follow verification workflows from a Simulink subsystem (Since R2020b)

Blocks

Assertion

Generate SystemVerilog assertions from Simulink assertion

Topics

Generate and Verify a DPI Component

DPI Component Generation with Simulink
If you have a Simulink Coder license, you can generate SystemVerilog DPI components using one of two methods.
SystemVerilog DPI Test Benches
Choose between the two types of SVDPI test benches.
Generate SystemVerilog DPI Component
Generate a DPI component from Simulink, and explore various configuration parameters.
Use Generated DPI Functions in SystemVerilog
How to export the generated DPI component to a SystemVerilog environment.
Verify Generated Component Against Simulink Data
Start ModelSim^® or Questa^® in GUI mode.
Generate SystemVerilog Assertions from Simulink Test Bench
Generate SystemVerilog assertions from your Simulink environment.

Advanced DPI Options

Generate Cross-Platform DPI Components
Generate a DPI component for an operating system different from your MATLAB^® host machine.
Customize Generated SystemVerilog Code
Describes how to customize the generated SystemVerilog code.
Tune Gain Parameter During Simulation
Generate a DPI component that provides tunable access to a parameter.
SystemVerilog DPI Component Test Point Access
You can designate internal signals in your model as test points and configure the SystemVerilog DPI generator to create one or more access functions.
Generate SystemVerilog Assertions and Functional Coverage
Generate SystemVerilog immediate assertions from verify statements and model verification blocks, and collect functional coverage information (requires Simulink Test™ license).

Verify Generated HDL Code with SystemVerilog DPI Test Bench (requires HDL Coder license)

Verify HDL Design Using SystemVerilog DPI Test Bench (HDL Coder)
This example shows how to use SystemVerilog DPI test bench for verification of HDL code where a large data set is required.
Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder)
Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.

Featured Examples

Build HDL Test Bench for QAM Transceiver Model

Build a behavioral test bench using SystemVerilog DPI-C component generation. This test bench is used for the verification of synthesizable HDL code of a 64-QAM transmitter and receiver.

Open Script

Verify Standalone CTLE in Architectural, Behavioral, and Circuit Domains

Simulates a continuous-time linear equalizer (CTLE) in several design domains, while keeping the underlying models in synchronization through tool automation. The Simulink® architectural model acts as a high-level specification of the desired analog circuit behavior. Using HDL Verifier™, export the standalone CTLE model into a SystemVerilog behavioral model. The exported model enables early digital control development for analog calibration before you design the analog circuit. A circuit implementation of the CTLE is characterized (offline) using analog simulations. The characterization results are then fed back into the architectural model. This converts the specification-based Simulink model into a circuit-representative model. Both specification and circuit-representative models of the CTLE are provided as part of this example. Use HDL Verifier to regenerate the SystemVerilog behavioral model. This model can be used for mixed-signal validation; turning the specification-based SystemVerilog model into a circuit-representative SystemVerilog model. This automation keeps the architectural, behavioral, and circuit models in synchronicity.

Open Live Script

Verify SerDes Toolbox CTLE in Architectural, Behavioral, and Circuit Domains

Demonstrates a workflow to simulate a continuous-time linear equalizer (CTLE) in several design domains, while keeping the underlying models in synchronization through tool automation.

Open Live Script

Verify Multi-Path ADC in Architectural, Behavioral, and Circuit Domains

Use a time-interleaved analog to digital converter (ADC) from Mixed-Signal Blockset™ to develop an offset and gain calibration engine for mismatched interleaved ADC paths. For an architectural representation of time-interleaved ADC for IBIS-AMI export, see the ADC IBIS-AMI Model based on COM and Architectural 112G PAM4 ADC-Based SerDes Model examples.

Open Live Script

Generate HDL for Dual-Summing-Node DFE

Design a bit-accurate decision feedback equalizer (DFE) adaptation engine for an architecturally representative 100-Gb/s dual-summing-node-DFE PAM4 SerDes receiver model using blocks from the SerDes Toolbox™. This bit-accurate DFE adaptation engine generates synthesizable RTL code that is suitable for implementation in an ASIC or an FPGA. The implementation-representative datapath in the DFE model enables the adaptation engine to reflect key design aspects: PAM4 threshold recovery, DFE tap weight adjustment, and clock phase sensitivity.

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Generate Bit Vector and Logic Vector Data Types

Generate bit or logic vector data types in the SystemVerilog interface of the DPI component. This capability is useful whenever having an exact width of the port is important to integrate the DPI component in your testbench.

Open Script

Getting Started with Customizing Generated SystemVerilog Code

Customize the generated SystemVerilog code in the SystemVerilog DPI Component Generation process.

Open Script

Generate Native SystemVerilog Assertions from Simulink

Generate native SystemVerilog assertions from assertions in a Simulink® model. This capability is useful whenever you need the same assertion behavior in Simulink and in your HDL testing environment.

Open Script

Generating Functional Coverage in SystemVerilog from Simulink Test verify Calls

Demonstrates how to test a projector control system using model simulation, and how to generate a SystemVerilog DPI component for some of the controller's high level requirements that are specified in a Test Sequence block. This will allow the requirement verification used for model simulation to be reused in the HDL simulator with minimal effort.

Open Script

Verify 5G Wireless Applications Using SystemVerilog DPI

Use SystemVerilog DPI components to verify 5G wireless applications in an HDL environment.

Open Model

Integrate SystemVerilog DPI into UVM Framework Workflow

Generate reusable verification components from a Simulink® model as SystemVerilog DPI components using HDL Verifier™ software. You use the MATLAB-to-UVMF (mtlb2uvmf) workflow to create Universal Verification Methodology (UVM) test benches quickly. For more information on mtlb2uvmf workflow, see MathWorks Integration from Siemens Verification Academy.

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