DPI Generation for MATLAB Code

Generate SystemVerilog DPI component from MATLAB^® code

To generate a DPI component from a MATLAB function, see Considerations for DPI Component Generation with MATLAB.

To use this functionality, download and install the ASIC Testbench for HDL Verifier add-on. This feature also requires MATLAB Coder™.

Functions

dpigen Generate UVM or SystemVerilog DPI component from MATLAB function

Objects

svdpiConfiguration Configure workflows for UVM and SystemVerilog component generation from MATLAB (Since R2023a)

Topics

Generate DPI Component Using MATLAB
This topic guides you through the workflow for creating a SystemVerilog DPI component from a MATLAB function.
Considerations for DPI Component Generation with MATLAB
You can export a MATLAB function as a component with a direct programming interface (DPI) for use in a SystemVerilog simulation.
Use Generated DPI Functions in SystemVerilog
How to export the generated DPI component to a SystemVerilog environment.
Use Variable-Sized Vector in SystemVerilog DPI Component
This example shows how to configure, generate, and use a SystemVerilog DPI (SVDPI) component with variable-length inputs or outputs.
SystemVerilog and UVM Template Engine
Generate customizable SystemVerilog modules and UVM components from MATLAB using templates.
Template Engine Language Syntax
Template variable definition and usage.

Featured Examples

Use Templates to Create SystemVerilog DPI and UVM Components

Generate SystemVerilog direct programming interface (DPI) and universal verification methodology (UVM) components from MATLAB® functions using built-in templates. This example also reviews the generated SystemVerilog and how it relates to the template. This example teaches you basic template capabilities, that you can use to create a custom template.

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Generate FIFO Interface DPI Component for UART Receiver

The full workflow of how to generate a SystemVerilog DPI component for a FIFO buffer interface meant to be integrated with a UART receiver. The interface is written in MATLAB, and exported to an HDL simulator. The SystemVerilog files for the UART receiver and its test bench are also provided.

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