Detect and Address Bugs

Detect run-time errors and logical errors, debug issues in your design

Simulink^® Design Verifier™ uses formal methods to identify hard-to-find design errors in models without requiring extensive tests or simulation runs. Design errors detected include runtime errors such as integer overflow, division by zero, and violations of design assertions and logical errors that indicate operating conditions that cannot occur. You use Simulink Design Verifier to highlight blocks in a model containing design errors and blocks proven to be without them. For each block with an error, you calculate signal-range boundaries and generate a test vector that reproduces the error in simulation.

Design Error Detection Basics

Featured Examples

Using Specified Input Minimum and Maximum Values as Constraints

Use input port minimum and maximum values as analysis constraints by Simulink® Design Verifier™ during both test generation and property proving.

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Detect Integer Overflow Errors

Detect integer overflow errors in a model by using design error detection analysis. Simulink® Design Verifier™ identifies the model constructs that may result in integer overflows and then either proves that the integer overflow cannot occur during simulation or generates test cases that demonstrates the integer overflow error.

Open Script

Detect Out of Bound Array Access Example Model

Detect out of bound array access errors in a model.

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Analyzing the Results for a Dead Logic Analysis

Demonstrates how to isolate potential causes of dead logic using the sldvexCommonCausesOfDeadLogic model. Dead logic detection finds unreachable objectives in the model that cause the model element to remain inactive.

Open Script

Detect and Address Bugs

Design Error Detection Basics

Categories

Featured Examples

Using Specified Input Minimum and Maximum Values as Constraints

Detect Integer Overflow Errors

Detect Out of Bound Array Access Example Model

Analyzing the Results for a Dead Logic Analysis