ASIC Testbench

Generate testbenches for ASIC and advanced FPGA designs

ASIC Testbench for HDL Verifier™ is an add-on that enables HDL Verifier to generate test components and verification models from MATLAB^® or Simulink^® into Universal Verification Methodology (UVM) or SystemVerilog environments. These models run natively in your HDL simulator.

Generate SystemVerilog Direct Programming Interface (DPI) components from MATLAB and Simulink. For more information, see SystemVerilog DPI Component Generation.
Generate UVM components or environments from MATLAB and Simulink. For more information, see UVM Component Generation Overview.
Export SystemC™ TLM-compatible transaction-level models from Simulink. For more information, see TLM Component Generation.

To use this functionality, download and install the ASIC Testbench for HDL Verifier add-on.

ASIC Testbench

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